As the operating voltages for CMOS transistor circuits have decreased, variations in the threshold voltages for the transistors have become more significant. Although low operating voltages offer the potential for reduced power consumption, gate threshold voltage variations due to process and environmental variables often prevent optimum efficiency and performance from being achieved due to increased leakage currents.
Threshold voltage variations may be compensated for by body-biasing. In typical CMOS transistors, the source of the transistor has a connection to the bulk region local to the transistor. This connection may be made to the substrate or to a well in the substrate containing the transistor. Body-biasing introduces a bias potential between the bulk and the source of the transistor that allows the threshold voltage of the transistor to be adjusted electrically.
Whereas the typical CMOS transistor is a three-terminal device, the body-biased CMOS transistor is a four-terminal device, and thus requires a more complex interconnect scheme. Connections for biasing may be made on the substrate surface using conventional metal/dielectric interconnects similar to those used for typical gate, drain, and source connections, or they may be made using buried complementary well structures.
For example, in a p-type substrate with a population of surface n-wells that contain p-channel field effect transistors (PFETs), a buried n-type layer may be formed in the substrate at a depth that allows for contact with the bottom of the N-wells, while providing sufficient clearance with respect to n-channel field effect transistors (NFETs) in the substrate.
Generally, prior art solutions assume that the resolvability of buried well features are of the same order as surface features. For example, some solutions teach forming apertures registered to transistor channel regions.
However, processes that try to form apertures in this way may end up with disconnected bits of buried N-well along with numerous width and spacing violations due to the size disparity between surface features and buried features.
The relative size of buried layer features is about an order of magnitude larger than surface features. With this built-in disparity, the mesh generating process and rules checking should accommodate a range of coverage and alignment issues not contemplated in the prior art. Thus, the prior art does not appreciate the disparity that exists in geometric sizes and spacing of buried substrate layers.